Synchronous Dynamic Random Access Memories (SDRAMs) are well known, and include such devices as Double Data Rate DRAMs (DDR DRAMs). In SDRAMs, and referring to FIG. 1A, data is written into and read out from the SDRAM 10 in synchronization with an external system clock signal (CLK). More specifically, when writing data to the array of cells 12 in the SDRAM 10, data is presented at the data lines (DQx) and at some discrete point during the clock's cycle—for example, on the clock's rising edge—this data enters the SDRAM 10 for eventual storage in the array 12 at an address specified by the address lines (Ax). Conversely, when reading data from the array 12, data is presented to the data lines (DQx) in accordance with the queried address on the address lines Ax, again at some discrete portion of the clock's cycle. Whether reading or writing is taking place is determined by the status of the row access strobe (RAS), column access strobe (CAS), chip select (CS), and write enable (W/E) signals (collectively, control signals 22) as is well known in DRAM technology. Ultimately these external control signals 22 are received from a system, such as a microprocessor system.
In an SDRAM, data can neither be written to nor read from the array 12 instantaneously. For example, it takes time for the data read from the array 12 to reach the data buffering circuit 19, which feeds data to the data lines DQx. For example, in a typical device, it takes approximately 15 nanoseconds (ns) for data to move from the array 12 and through the data buffering circuitry 19 to the data lines DQx when a read has been initiated. Thus, and referring to FIG. 1B, if the system clock signal CLK has a period (p) of 3 ns, and if a read request is specified at time T0 at a first address (addr 1), the data from that address will appear at the data lines DQx after five clock cycles at T5. Accordingly, the device is said to have a “read latency” (or Column Access Strobe (CAS) latency) of five clock cycles or just “five” for short. As is typical, particularly in DDR SDRAMs, the presentation of the data at the data lines will be preceded by the presentation of a data strobe signal DQS, which generally informs the microprocessor system to prepare for the data to be presented on the next cycle—what is known as the one cycle “read preamble.” Hence, if the read latency is five, the DQS signal will issue one cycle before, or at cycle T4 in this example. Prior to the assertion of the DQS signal, the DQS is tri-stated.
The read latency for a given SDRAM and for a given external clock signal CLK period p is generally a parameter specified by the manufacturer of the SDRAM, and can generally be programmed by the user within some range. In any event, once the read latency was set, the read performance of SDRAMs in view of the read latency was generally predictable in the prior art. Because it was predictable, simple solutions were used for determining when to enable the transfer of the data and the data strobe from the data buffering circuit 19 to the output circuitry 20 (which includes the output latches or buffers 20), and when to enable (i.e., non-tri-state) the outputting of the data and data strobe from the output circuitry 20 to the data lines DQx. For example, output enable registers 14 were used between the decoder block 16 and the output circuitry 20 to clock the internal read signal (IR) through the registers to ultimately generate an output enable data signal (QED) and an output enable strobe signal (QES; which precedes QED by one cycle because of the read preamble). For example, if the read latency was six, then five output enable registers 14 would be used such that the internal read signal (IR), when clocked through, would generate a QED signal on the fifth clock cycle. This QED signal would then appear at the data buffering circuitry 19 and at the output circuitry 20 to start clocking the data to the data lines DQx at the sixth clock cycle. (Only five registers 14 would be needed as the output buffers 20 essentially comprise the sixth latch). A QES signal would likewise enable the issuance of the data strobe on line DQS on the fifth clock cycle.
Clocking of the output enable registers 14, the data buffering circuit 19, and the output circuitry 20 occurred in conjunction with an internal clock, DLLR, generated from the external clock CLK by a delay locked loop (DLL) circuit 18. Typically in the prior art, the internal clock DLLR was adjusted to lead the external clock CLK by the propagation delay of the output circuitry 20. In this way, when the outputs were enabled, the timing lead was subtracted by virtue of the delay, such that the data was output to data lines DQx (and the data strobe was output to line DQS) in synchronization with the external clock.
As clock times increase and as their periods p decrease, effects not noticeable at slower clock speeds are becoming apparent and significant, and make it difficult to read data out of an SDRAM with predictability and in accordance with the specified read latency. For example, consider assessment of the control signals 22 used (among other functions) to inform the device 10 to begin reading. This assessment requires decoding of the control signals 22 at decoder block 16, which ultimately outputs the internal read signal (IR) that informs the device that it is now in a read status. In the prior art, the time required to decode the control signals 22 (perhaps 2 ns) was small compared to the period p of the clock. Thus, it could be assured that the internal read command IR would issue within the same clock cycle that the read command was issued externally to the device via control signals 22.
By contrast, in current technologies and those on the near horizon, the time required to decode the control signals 22 at the decoder block 16 could take more than a single clock cycle, thus making the number of cycles between issuance of the external control signals 22 and generation of the internal read signal IR less predictable. Adding to this uncertainty, the propagation delay in the decoder block 16 is variable, and specifically can vary with changes in the Process used to form the device, the Voltage at which the device is operated, and the Temperature at which the device is operated (i.e., PVT variations). Thus, depending on the PVT conditions, generation of the internal read signal IR could take 1, 2 or 3 cycles, for example.
Furthermore, it is also important to note that the propagation delay of the output circuitry 20 (See FIGS. 1A and 3) is also subject to the same issue of variability. Therefore, depending on PVT variations and the clock cycle time, DLLR may also lead the external clock by one or more cycles, further complicating the problem of generating properly timed output enable signals.
Because these propagation delays can change in numbers of clock cycles, the number of fixed output enable registers 14 needed for proper alignment with the read latency would also need to change. It is thus becoming increasingly more difficult to use a fixed solution such as enablement of a fixed number of output enable registers 14. Simply put, given PVT variations, it is not certain how many output enable registers 14 would be needed at any particular time. As a result, read data cannot be provided at the output lines DQx with the accuracy required by the specified read latency.
Accordingly, the art would be benefited by a solution to this problem, and this disclosure provides such a solution.